1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, a semiconductor device and a method of manufacturing a semiconductor device I including steps of fabricating a capacitor.
2. Description of the Prior Art
There is an FeRAM (Ferroelectric Random Access Memory) as the nonvolatile semiconductor memory device. The FeRAM comprises a capacitor having a high-ferroelectric film and a memory cell formed of an n-type MOS transistor. As such high-ferroelectric material, PZT, PLZT, etc. which have a perovskite structure, for example, are employed. Such high-ferroelectric film is formed by the sputtering method, the CVD method, the sol-gel process, etc. Since the high-ferroelectric film must be oxidized and crystallized in the high-temperature oxygen atmosphere, platinum (Pt), ruthenium (Ru), iridium (Ir), or the like, which is difficult to be oxidized or which does not lose conductive property even if oxidized, is employed as electrode material.
PZT is short for lead zirconate titanate (Pb(Zr.sub.x Ti.sub.1-x)O.sub.3). PLZT is PZT in which lanthanum is added, and its chemical formula is Pb.sub.y La.sub.1-y (Zr.sub.x Ti.sub.1-x)O.sub.3.
By way of example, the semiconductor memory device employing the high-ferroelectric capacitor is manufactured by the steps described in the following.
First, as shown in FIG. 1A, an n-type MOS transistor 2 is formed on a silicon substrate 1. The n-type MOS transistor 2 is formed in a region which is surrounded by a device isolation insulating layer 6 on a surface of the silicon substrate 1. The n-type MOS transistor 2 comprises a gate electrode which is formed on the silicon substrate 1 via a gate insulating film 3, and a source region 5s and a drain region 5d which are formed in the silicon substrate 1 on both sides of the gate electrode 4.
The gate electrode 4 constitutes a part of a word line WL, and remaining portion of the word line WL is positioned to pass through on the device isolation insulating layer 6.
After the n-type MOS transistor 2 and the word line WL have been formed, an interlayer insulating film 7 is formed to cover the n-type MOS transistor 2, the word line WL, etc., as shown in FIG. 1B.
Then, steps needed until a configuration shown in FIG. 1C is formed will be explained hereunder.
A first platinum (Pt) layer 8 and a PZT layer 9 are then grown in sequence on the interlayer insulating film 7 over the device isolation insulating layer 6 which is formed adjacent to the n-type MOS transistor 2. A resultant structure is then annealed in the oxygen atmosphere to crystallize the PZT layer 9. A second platinum layer 10 is then formed on the PZT layer 9.
After this, the second platinum layer 10 is patterned by using the photolithography technology which employs an etching gas and a resist mask. The patterned second platinum layer 10 is employed as an upper electrode of the capacitor.
The PZT layer 9 is then patterned by using the photolithography technology to shape a dielectric layer of the capacitor. A lower electrode of the capacitor is then formed by patterning the first platinum layer 8 by using the photolithography technology.
With the above, patterning of the capacitor has been completed.
A protection insulating film 11 formed of SiO.sub.2 is then grown on an overall surface by the chemical vapor deposition using TEOS (Tetraethoxysilane). As shown in FIG. 1D, a first opening portion 11a and a second opening portion 11b are then formed by patterning the protection insulating film 11 such that the second platinum layer (upper electrode) 10 is exposed from the first opening portion 11a and also the first platinum layer (lower electrode) 8 is exposed from the second opening portion 11b.
As shown in FIG. 1E, a third opening portion 11g, a fourth opening portion 11d, and a fifth opening portion 11s are then formed by patterning the protection insulating film 11 and the interlayer insulating film 7 to expose the gate electrode (word line WL), the drain region 5d, and the source region 5s respectively.
In turn, an aluminum layer is formed on an overall surface. As shown in FIG. 1F, wirings 12a, 12b, 12s, 12d, 12g made of aluminum are then formed by patterning the aluminum layer by using the photolithography.
The above steps have been set forth in Patent Application Publication (KOKAI) hei 8-37282, for example, etc.
In the semiconductor memory device having the above-mentioned configuration, the capacitor is heated and exposed to the reduction atmosphere inevitably in the step of forming the protection insulating film 11, the step of forming the opening portions 11a, 11b, etc. to reduce residual polarization charge in the PZT layer 9. Therefore, electric characteristics of the capacitor are degraded.
The upper electrode 10 is ready to peel if it is subjected to the step of forming the protection insulating film 11 and various subsequent steps.